Chip Design ML papers, 2023–2026

Key findings

• Chip Design ML went from 28 papers in 2023 to 64 in 2026, roughly 2.3x in three years.
• NeurIPS publishes the most Chip Design ML work: 83 papers from 2023 to 2026, 46% of the four-venue total.
• The fastest-growing overlap is with Diffusion Models: papers tagged with both rose from 0 in 2023 to 9 in 2026.
• Among the 5 topics under Hardware and Compilers, it ranks #2 by 2026 paper count; the fastest grower in the group, Edge Inference, is up 4.0x versus 2.3x here.

Representative papers

Spread across years and venues so every edition shows up

• NeurIPS 2026ChiP-STAR: Spatial-Topological Attention for Pre-trained Generative Chip Routing
• ICML 2026Order Matters: Unveiling the Hidden Impact of Macro Placement Sequences via Proxy-Guided LLM Evolution
• ICLR 2026How Muon’s Spectral Design Benefits Generalization: A Study on Imbalanced Data
• CVPR 2026PSDesigner Automated Graphic Design with a Human-Like Creative Workflow
• NeurIPS 2025MIHC: Multi-View Interpretable Hypergraph Neural Networks with Information Bottleneck for Chip Congestion Prediction
• ICML 2025Probabilistic Factorial Experimental Design for Combinatorial Interventions
• ICLR 2025LaMPlace: Learning to Optimize Cross-Stage Metrics in Macro Placement
• CVPR 2025From Elements to Design: A Layered Approach for Automatic Graphic Design Composition
• NeurIPS 2024AFBench: A Large-scale Benchmark for Airfoil Design
• ICML 2024A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design
• ICLR 2024CircuitNet 2.0: An Advanced Dataset for Promoting Machine Learning Innovations in Realistic Chip Design Environment
• CVPR 2024Discontinuity-preserving Normal Integration with Auxiliary Edges
• NeurIPS 2023Circuit as Set of Points
• ICML 2023AbODE: Ab initio antibody design using conjoined ODEs
• ICLR 2023Neural Design for Genetic Perturbation Experiments
• CVPR 2023Visibility Constrained Wide-Band Illumination Spectrum Design for Seeing-in-the-Dark
• NeurIPS 2026DiffCool: Label-Free Synthesis of Chip-Tailored Heat Sinks via Thermal-Aware Diffusion
• ICML 2026Axiomatic Atlas: A Prescriptive Framework for Neural Architecture Design
• ICLR 2026Topology Matters in RTL Circuit Representation Learning
• CVPR 2026FEAT Fashion Editing and Try-On from Any Design

All Chip Design ML papers

179 papers, page 2 of 4

51. NeurIPS 2026PCBInnoBench: Benchmarking LLM Agents on Real-World PCB Design
52. NeurIPS 2026Principled Design of Diffusion-based Optimizers for Inverse Problems
53. NeurIPS 2026Refactoring Code Through Library Design
54. NeurIPS 2026Regret Minimization in Single-Dimensional Contract-Design with Binary Actions
55. NeurIPS 2026Robust-by-Design Distributional Learning from Contaminated Samples
56. NeurIPS 2026Sample Size Design for Bounds on Discrete Probabilities of Causation
57. NeurIPS 2026Scattered by Design: Why Per-Output Pruning Resists Structured Compression
58. NeurIPS 2026Selectivity and Shape in the Design of Forward-Forward Goodness Functions
59. NeurIPS 2026SimpleEvol: Efficient Intelligence Conversion via Less Human Prior in Automated Heuristic Design
60. NeurIPS 2026The Alternation Depth Principle for Neural Operator Design
61. NeurIPS 2026The Design Space of Tri-Modal Masked Diffusion Models
62. NeurIPS 2026VEHBench: A Stage-Local Diagnostic Benchmark for LLM-Assisted Vibration Energy Harvester Design
63. NeurIPS 2026When Does Knowing the State Help? Diagnosing Process vs. Outcome Reward Design
64. NeurIPS 2026μLM: Rethinking Sub-100M Language Models through Memory-First Design
65. CVPR 2025BlueLM-V-3B: Algorithm and System Co-Design for Multimodal Large Language Models on Mobile Devices
66. CVPR 2025CADCrafter: Generating Computer-Aided Design Models from Unconstrained Images
67. CVPR 2025CASAGPT: Cuboid Arrangement and Scene Assembly for Interior Design
68. CVPR 2025Effective Cloud Removal for Remote Sensing Images by an Improved Mean-Reverting Denoising Model with Elucidated Design Space
69. CVPR 2025From Elements to Design: A Layered Approach for Automatic Graphic Design Composition
70. CVPR 2025Rethinking Decoder Design: Improving Biomarker Segmentation Using Depth-to-Space Restoration and Residual Linear Attention
71. ICLR 2025Bayesian Experimental Design Via Contrastive Diffusions
72. ICLR 2025Charting the Design Space of Neural Graph Representations for Subgraph Matching
73. ICLR 2025CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
74. ICLR 2025DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale
75. ICLR 2025EVA: Geometric Inverse Design for Fast Protein Motif-Scaffolding with Coupled Flow
76. ICLR 2025FreeCG: Free the Design Space of Clebsch-Gordan Transform for Machine Learning Force Fields
77. ICLR 2025gRNAde: Geometric Deep Learning for 3D RNA inverse design
78. ICLR 2025LaMPlace: Learning to Optimize Cross-Stage Metrics in Macro Placement
79. ICLR 2025LASeR: Towards Diversified and Generalizable Robot Design with Large Language Models
80. ICML 2025Chip Placement with Diffusion Models
81. ICML 2025Contract Design Under Approximate Best Responses
82. ICML 2025EGPlace: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation
83. ICML 2025Fraud-Proof Revenue Division on Subscription Platforms
84. ICML 2025Optimal Auction Design in the Joint Advertising
85. ICML 2025Probabilistic Factorial Experimental Design for Combinatorial Interventions
86. ICML 2025Reliable Algorithm Selection for Machine Learning-Guided Design
87. ICML 2025Safely Learning Optimal Auctions: A Testable Learning Framework for Mechanism Design
88. ICML 2025Simple Randomized Rounding for Max-Min Eigenvalue Augmentation
89. NeurIPS 2025A Cramér–von Mises Approach to Incentivizing Truthful Data Sharing
90. NeurIPS 2025Adaptive Kernel Design for Bayesian Optimization Is a Piece of CAKE with LLMs
91. NeurIPS 2025Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms
92. NeurIPS 2025Convergent Functions, Divergent Forms
93. NeurIPS 2025Ctrl-DNA: Controllable Cell-Type-Specific Regulatory DNA Design via Constrained RL
94. NeurIPS 2025Design-Based Bandits Under Network Interference: Trade-Off Between Regret and Statistical Inference
95. NeurIPS 2025Efficient Bayesian Experiment Design with Equivariant Networks
96. NeurIPS 2025Exploring the Design Space of Diffusion Bridge Models
97. NeurIPS 2025Geometric Algebra-Enhanced Bayesian Flow Network for RNA Inverse Design
98. NeurIPS 2025Hadamax Encoding: Elevating Performance in Model-Free Atari
99. NeurIPS 2025Mechanism Design via the Interim Relaxation
100. NeurIPS 2025MIHC: Multi-View Interpretable Hypergraph Neural Networks with Information Bottleneck for Chip Congestion Prediction

FAQ

How many Chip Design ML papers were published at NeurIPS, ICLR, ICML and CVPR from 2023 to 2026?

179 in total: 28 in 2023, 43 in 2024, 44 in 2025, 64 in 2026.

How many Chip Design ML papers are at NeurIPS 2026?

NeurIPS 2026 has 34 Chip Design ML papers, versus 20 the year before.

How many Chip Design ML papers are at ICLR 2026?

ICLR 2026 has 9 Chip Design ML papers, versus 9 the year before.

How many Chip Design ML papers are at ICML 2026?

ICML 2026 has 18 Chip Design ML papers, versus 9 the year before.

How many Chip Design ML papers are at CVPR 2026?

CVPR 2026 has 3 Chip Design ML papers, versus 6 the year before.

Which conference publishes the most Chip Design ML papers?

NeurIPS, with 83 papers from 2023 to 2026.