AnalogToBi: Device-Level Analog Circuit Topology Generation via Bipartite Graph and Grammar Guided Decoding

Abstract

Analog circuit design remains highly dependent on expert knowledge due to the complexity of device-level interactions and topology design. Recent transformer-based approaches for device-level topology generation have shown promise, yet they suffer from low electrical validity without human-in-the-loop (HITL) training and severe memorization caused by sequence-based circuit representations. In this work, we propose **AnalogToBi**, a framework for device-level analog circuit topology generation. AnalogToBi introduces *circuit-type conditioning* for categorizing heterogeneous multi-type topology datasets, *device renaming augmentation* to mitigate memorization, *a bipartite graph representation* for improved structural generalization, and *grammar-guided decoding* to enforce structural validity during bipartite graph generation. Experimental results demonstrate that AnalogToBi achieves high validity and novelty without HITL training while effectively avoiding memorization of training topologies.